A self-reconfiguration architecture for mesh arrays

Recent advances in VLSI technology has stimulated research in massively parallel computers to satisfy the continuously increasing demand for computer power in advanced science and technology applications. Mesh-interconnection is one of the most attractive interconnections and architectures for massively parallel computers. This paper addresses a new reconfigurable architecture to implement massively parallel mesh-arrays on a silicon wafer by wafer scale integration (WSI), which is expected as a promising technology to construct massively parallel computers on silicon wafers. The performance of the proposed scheme is discussed with respect to system yield. It is confirmed that the reconfigurable architecture without global information on the fault distribution achieves the same system yield as the earlier designs based on a graph theory which requires global information.