A generic nonlinear output error structure implemented on a PWL ASIC

In this paper, we present a Nonlinear Output Error (NOE) model structure implemented on an Application Specific Integrated Circuit (ASIC) chip dedicated to Piecewise Linear (PWL) calculation. Three examples are included to show the performance of the ASIC in quantization, truncation and fixed-point operation. Experimental results and simulation results are shown and compared.