Algorithm-Enhanced Retention Based on Megabit Array of $\hbox{Cu}_{x}\hbox{Si}_{y}\hbox{O}$ RRAM

Robust retention is achieved on 1-Mb Cu
_x
Si
_y
O resistive random access memory test chip. The Ron retention fail bits can be effectively improved by enhanced set algorithm. The baking failure rate is less than 9 ppm after baking at 125°C for 1000 h under set algorithm (CC = 25 μA, PA = 2 V, and PD = 100 ns). R
_on
resistance can be used as retention criterion in production screening whatever the algorithm is. The mechanism of retention enhanced by algorithm is proposed based on the conductive filament model.