Quick characterization of statistical variations and sensitivity for speed and power consumption within a wafer of sub-micron CMOS

It has presented the statistical performance from a focus on the minimum gate length of 0.8 /spl mu/m devices and CMOS ICs. The CMOS performances based on intra-die statistics have been statistically evaluated through experimental data gathered from four-type CMOS circuits. Most of measurements indicate higher speeds and larger powers at the edge positions of the wafer than at the central ones of the wafer, checking for real process maturity by discerning any outliers of the spec range which is speculated from variations as percentiles. This relationship of tradeoff between speed and power at those positions is true when the gate oxide thickness varies. Further, mixed-mode current-mirror CMOS circuit shows the large variations because of the poly resistor which separates the bias between MOSFET transistors.