A Design Methodology for Power Efficiency Optimization of High-Speed Equalized-Electrical I/O Architectures

Both power efficiency and per-channel data rates of high-speed input/output (I/O) links must be improved in order to support future inter-chip bandwidth demand. In order to scale data rates over band-limited channels, various types of equalization circuitry are used to compensate for frequency-dependent loss. However, this additional complexity introduces power and area costs, requiring selection of an appropriate I/O equalization architecture in order to comply with system power budgets. This paper presents a design flow for power optimization of high-speed electrical links at a given data rate, channel type, and process technology node, which couples statistical link analysis techniques with circuit power estimates based on normalized transistor parameters extracted with a constant current density methodology. The design framework selects the optimum equalization architecture, circuit logic style (CMOS versus current-mode logic), and transmit output swing for minimum I/O power. Analysis shows that low loss channel characteristics and minimal circuit complexity, together with scaling of transmitter output swing allows excellent power efficiency at high data rates.