A unified approach to the synthesis of fully testable sequential machines

An attempt is made to unify and extend the various approaches to synthesizing fully testable sequential circuits that can be modeled as finite state machines (FSMs). The authors first identify classes of redundancies and isolate equivalent-state redundancies as those most difficult to eliminate. It is then shown that the essential problem behind equivalent-state redundancies is the creation of valid/invalid state pairs. The remainder of this research is devoted to techniques for developing differentiating sequences for valid/invalid state pairs created by a fault, as well as to techniques for retaining these sequences in the presence of that fault. A variety of techniques have been proposed to address this problem. At one end of the spectrum there are optimal synthesis procedures that ensure full testability by eliminating redundancies via the use of appropriate don't care sets. At the other end of the spectrum there are constrained synthesis procedures that produce fully and easily testable sequential circuits by restricting the implementation of the logic. The notion of fault-effect disjointness is used to explore the landscape between these two extremes and a spectrum of methods that place relatively more-or-less emphasis on either logic optimization or constrained synthesis is demonstrated. Techniques used in this exploration include fault simulation, Boolean covering, algebraic factorization, and state assignment. Experimental results using the proposed synthesis procedures and comparisons to previous approaches are presented.<
>