A hexagonal array machine for multilayer wire routing

A novel hardware accelerator comprised of several fast processors interconnected in the form of a hexagonal mesh with wraparound connections is proposed. The novelty of the proposed architecture stems from the fact that it is suitable not only for single-layer routing, but also for routing in parallel on multiple layers. A hexagonal machine of dimension square root kG, with about 3kG processors, can handle a k-layer grid consisting of kG/sup 2/ grid points at about the same speed as a full-grid machine with kG/sup 2/ processors. A technique for measuring the performance of a hardware accelerator in terms of the average delay incurred over a full-grid machine is suggested. This has been formalized in the case of the hexagonal architecture, and is presented for various nets and mesh dimensions. The results have been accurately verified by extensive simulation done in C++ language. It is demonstrated that the hexagonal mesh, by virtue of its additional links for expansion, is resilient to about 10% of failure in the links and processing elements. A detailed design for a chip implementation of the hexagonal machine is discussed.<
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