Novel overshoot cancellation in comparator-based pipelined ADC

In this paper, a new overshoot cancellation method is presented for comparator-based pipelined ADCs. By introducing charging and discharging operations in two adjacent stages, the large overshoot in each stage can be either tolerated as sub-ADC error or cancelled out with each other. Applying this concept, a 10-bit pipelined ADC has been designed and simulated in a 0.18-μm CMOS process. It achieves 57.2dB SNDR at 20MS/s and consumes 2.6mW under 1.8 V supply, resulting in an ENOB of 9.2-bit and an FOM of 0.221 pJ/Conv.-step.