A power-efficient sizing methodology of SAR ADCs

Analog-to-digital converter (ADC) is a vital component for modern electronic systems, but designing an ADC usually takes much time and effort. Though several synthesis methods have been presented for analog circuits, there exists limited works focusing on ADC design automation. In this paper, we propose a systematic sizing methodology to minimize the power consumption for successive approximation register (SAR) ADCs in transistor level. This method manipulates the characteristics of SAR ADC to develop an efficient searching algorithm for shortening the sizing time. The time complexity of our method is O(2 log
₂
|S|), where jSj is the number of candidates in the searching space. According to the proposed sizing flow, we develop a sizing tool which is independent of manufacturing process and is able to minimize power consumption for SAR ADCs. By using the developed sizing tool, a proof-of-concept prototype was carried out within only 15 minutes and fabricated in a 1P4M 0.11μm process. The measurement results show the prototype demonstrates a high competitiveness compared to other state-of-the-art works on performance and power efficiency.