A novel current-mode ultra low power analog CMOS four quadrant multiplier

A novel CMOS current mode analog multiplier is presented. The design is based on using MOSFET operating in subthreshold region to achieve ultra low power dissipation. The circuit is operated from ± 0.75V DC supply. The proposed circuit has been simulated using Tanner in 0.35μm TSMC CMOS process. Simulation results show that the total power dissipation is 2.3μW, total harmonic distortion is 0.7%, maximum linearity error is 0.3% and the bandwidth is 2.8MHz.