Enhanced Operation in Charge-Trapping Nonvolatile Memory Device With $\hbox{Si}_{3}\hbox{N}_{4}/\hbox{Al}_{2}\hbox{O}_{3}/\hbox{HfO}_{2}$ Charge-Trapping Layer

A stacked Si
₃
N
₄
/HfO
₂
charge-trapping (CT) layer was proposed to improve erase operation and retention for CT nonvolatile memory (NVM) devices. The improvement can be attributed to the smaller valence band offset of Si
₃
N
₄
to Si and the higher barrier for electron detrapping from HfO
₂
to Si
₃
N
₄
. The programming and retention characteristics of CT NVM devices can be further enhanced by inserting Al
₂
O
₃
between Si
₃
N
₄
and HfO
₂
as the CT layer. This is because most of the injecting charges are trapped at the Si
₃
N
₄
/Al
₂
O
₃
interface, and Al
₂
O
₃
also provides a high barrier for electron detrapping.