Multithreaded systolic/SIMD DSP array processor-MUS2DAP

This paper deals with architectural design of the systolic/SIMD DSP processing array called MUS2DAP optimized for the execution of DSP filtering, vector/matrix and linear algebra algorithms. Its main features are architectural support for multithreading, interprocessor communication based on virtual channels and exploitation of instruction level parallelism within each processing cell of the array. Up to four threads can be executed in an interleaved fashion on one processor array. Physical implementation details of the processor network topology are hidden from programmer, since instructions used for interprocessor communication operate on virtual channels. The same algorithm can thus be executed unchanged on multiple physically implemented interconnection network topologies ranging from linear, 2D mesh to hex array. Architecture is optimized to execute algorithms in single precision 32-bit floating-point arithmetic. There are two controllers available, each controlling part of the processing array. This feature is helpful in implementing linear algebra algorithms which usually have processing cells with different functionalities within single array.