ESD protection networks for 3D integrated circuits

The inter-die signal interfaces in a 3D-IC are vulnerable to over-voltage stress induced by Charged Device Model ESD. The magnitude of the stress is highly sensitive to the design of the ground distribution network on both the die and package level. It is also affected by the type of package being used. Small voltage clamping devices may be placed at inter-die receivers to mitigate the risk of gate dielectric breakdown. New ESD rule checking tools are needed for 3D-IC design automation.