Efficient code generation for digital signal processors with parallel and pipelined instructions

Modern digital signal processors are capable of performing multiple pipelined instructions concurrently. However, strict and complicated coding rules, mostly due to the limitation of the processor's internal structures, must be observed to achieve the full performance. These include the proper selection of operand data types, efficient usage of data and address registers, and novel instruction scheduling to support parallel execution without pipeline conflicts. In this paper, a progressive code generation scheme based on a simulated evolution algorithm is devised. In this scheme, the selection of operand data type is embedded in instruction scheduling so that appropriate choices can be made to support parallel instruction. Instruction scheduling and register allocation, however, are performed in an interleaving and iterative manner. In each iteration, the generated code quality is evaluated and the inferior part is rescheduled. Tested benchmark programs indicate that our scheme can outperform the TI DSP processor C compiler and generate very efficient assembly codes.