Design and implementation of a complex multiplier using distributed arithmetic

We propose an efficient scheme for implementing a complex multiplier based on distributed arithmetic. A modified bit-serial shift-accumulator for distributed arithmetic is also proposed for computing a*b+c, where a, b and c are complex numbers. The shift-accumulator is highly regular and modular and consists of only three types of bit-slices, each of which consists of only three types of blocks, multiplexers, exclusive OR gates, and latches. The implementation is done using a robust differential single-phase clocked logic style suitable for high-speed and low power operation. The resulting implementation of the complex multiplier has a maximum clock frequency of 250 MHz, consumes 70 mW, and occupies a chip area of 0.5 mm/sup 2/ in a double-metal 0.8 /spl mu/m process. The coefficient word length and the data word length are 12 bits and 16 bits, respectively.