Topological synthesis of clock trees for VLSI-based DSP systems

This paper considers the problem of designing the topology of a clock distribution network for a synchronous digital signal processor so as to satisfy a non-zero clock skew schedule. A methodology and related algorithms for synthesizing the topology of the clock distribution network from a clock schedule derived from circuit timing information are presented. A new formulation of the problem of designing the clock distribution network is given as an efficiently solvable integer linear programming (ILP) problem. The proposed approach is demonstrated on the suite of ISCAS'89 benchmark circuits. Up to a 64% performance improvement is attained on these circuits by exploiting non-zero clock skew throughout the synchronous system. Clock tree topologies that implement the non-zero clock skew schedule based on the synthesis algorithms presented in this paper are described for each of the benchmark circuits.