An event-driven, alias-free ADC with signal-dependent resolution

A clockless 8b ADC in 130nm CMOS uses a time-varying comparison window to dynamically vary resolution, and input-dependent dynamic bias, to maintain SNDR while saving power. Alias-free operation with SNDR in the range of 47-54dB, which partly exceeds the theoretical limit of 8b conventional converters, is achieved over a 20kHz bandwidth with 3-9μW power from a 0.8V supply.