Efficiency of mechanical stressors in Planar FDSOI n and p MOSFETs down to 14nm gate length

We fabricated highly stressed Fully Depleted Silicon-On-Insulator (FDSOI) n and pMOSFETs reaching I
_ON,n
/I
_ON,p
=1148/1014μA/μm drive current at I
_OFF,n
/I
_OFF,p
=55/16nA/μm leakage current (V
_DD
=1V) with excellent V
_T
-matching (A
_VT
<; 1.5mV.μm). These short channel performances are well correlated and quantitatively explained by the effectiveness of strained SOI (sSOI), Contact-Etch-Stop-Layers (CESL) and SiGe raised sources and drains. sSOI improves I
_ON,n
up to 22% and degrades SiGe sources and drains efficiency for pMOSFETs. However, 0° (<;110>;) orientation remains the best configuration for high-stress pMOSFETs and provides the best trade-off for CMOS.