Process control & integration options of RMG technology for aggressively scaled devices

We report on aggressively scaled RMG-HKL devices, with tight low-V
_T
distributions [σ(V
_Tsat
) ~ 29mV (PMOS), ~ 49mV (NMOS) at L
_gate
~35nm] achieved through controlled EWF-metal alloying for NMOS, and providing an in-depth overview of its enabling features: 1) physical mechanisms, model supported by TCAD simulations and analysis techniques such as TEM, EDS; 2) process optimizations implementation: oxygen sources reduction, control of RF-PVD TiAl/TiN ratio and reduced H
_gate
, also impacting stress induced in the channel. Additional key features: 1) Al vs. W as fill-metal, with careful liner/barrier materials selection and tuning yielding well-behaved devices with tight R
_gate
distributions down to L
_gate
~20nm, and enabling both PMOS and NMOS low-VT values for high aspect-ratio gates (H
_gate
~60nm, L
_gate
≥30nm); 2) wet-etch vs. siconi clean for dummy-dielectric removal, with HfO
₂
post-deposition N
₂
-anneal resulting in substantial BTI improvement without EOT or low-field/peak mobility penalty, and good noise response.