A CMOS spectrum analyzer frontend for cognitive radio achieving +25dBm IIP3 and −169 dBm/Hz DANL

A dual RF-receiver preceded by discrete-step attenuators is implemented in 65nm CMOS and operates from 0.3–1.0 GHz. The noise of the receivers is reduced by cross-correlating the two receiver outputs in the digital baseband, allowing attenuation of the RF input signal to increase linearity. With this technique a displayed average noise level below −169 dBm/Hz is obtained with +25 dBm IIP
3
, giving a spurious-free dynamic range of 89 dB in 1 MHz resolution bandwidth.