Temperature dependence of soft error rate in flip-flop designs

The factors affecting the temperature dependence of soft error rates (SER) in flip-flops are investigated. Four different flip-flop designs with varying hardness levels were designed and fabricated in a 40 nm bulk CMOS technology. Neutron experiments show an increase in soft error (SE) failure in time (FIT) rate of over 3X for a temperature range of 25 °C - 110 °C. Alpha experiments show 1.5X increase in SE FIT rate for the same temperature range.