Performance analysis of parallel frame synchronization scheme in SDH systems

We analyze the performance of a new parallel frame synchronization system used for SDH networks. The performance is measured by using false synchronous probability P/sub FS/, the average synchronous incoming time T/sub ASI/, the average synchronous catching time T/sub ASC/, and the average synchronization holding time T/sub ASH/. Analysis indicates that the performance of our scheme is similar to that of the traditional approaches, or better under some condition. Furthermore, our scheme permits designers to use off-the-shelf integrated circuits to build SDH synchronization system.