A performance model for ATM switches with multiple input queues

An analytical model for the performance analysis of a novel input access scheme for an ATM switch is developed and presented in this paper. The interconnection network of the ATM switch is internally nonblocking and each input port maintains a separate queue for each output port so as to reduce the head-of-line (HOL) blocking of conventional input queuing switches. Each input is allowed to send only one cell per time slot, and each output port is allowed to receive only one cell per time slot. Using a tagged queue approach, an analytical model with an underlying two-dimensional Markov chain with a state space of size (queue capacity/spl times/switch size) is constructed for evaluating the switch performance under i.i.d Bernoulli traffic for different offered traffic loads. The switch throughput, mean cell delay, and cell loss probability are computed from the analytical model. The accuracy of the analytical model is verified using simulation.