Design of a low power 2GHz CMOS frequency divider for WSN applications

A 2 GHz programmable frequency divider is presented in this paper for Chinese and American band WSN applications. The divide ratio can be programmed from 720 to 960. The divider basically consists of a 15/16 dual-modulus prescaler and a programmable pulse-swallow counter. Forward phase switching technique is used to reduce power consumption and avoid glitches. Designed in 0.18-μm CMOS process, the 15/16 prescaler and pulse-swallow occupies a chip area of approximately 60 μm * 90 μm and 85 μm * 85 μm. The post-layout simulation shows that the divider can operate under input frequency ranging from 1GHz to 3GHz and consume 3.24 mW from a single 1.8V supply.