A NMOS bulk voltage trimming offset calibration technique for a 6-bit 5GS/s Flash ADC

In this work a new high-resolution offset cancellation technique based on bulk-voltage trimming is presented, which can be applied to Flash analog-to-digital converters (ADCs). The offset calibration is achieved by digitally adjusting the bulk voltages of the differential pairs of the preamplifier consisting of NMOS transistors in a triple well technology. Furthermore this technique minimizes the power consumption using only one power supply. A 6-bit, 5GS/s Flash ADC is implemented in 1.2V 90nm CMOS process. Using proposed calibration technique, an input-referred sigma offset of 0.09 LSB compared to 1.8 LSB without the calibration is achieved.