Yield learning in integrated circuit package assembly

This paper describes a yield learning model for integrated circuit package assembly. The goal was to provide a management tool for making yield projections, resource allocations, understanding operating practices, and performing what-if analyses. The model was developed using a series of case studies of packages entering manufacturing. These studies were a tape carrier package (TCP) at Intel, Chandler, AZ, a ceramic ball grid array (CBGA) and plastic quad flat pack (PQFP) at IBM, Bromont, P.Q., Canada, and a plastic ball grid array (PBGA) at Motorola, Austin, TX. These packages covered a wide range of technologies, including liquid and overmolded encapsulation, wirebond and controlled collapsed chip connection (C4) chip connections, and tape automated bonding (TAB), ceramic, laminate, and leadframe substrates. The factors that affect yield learning rates (e.g., process complexity, production volumes, personnel experience) were identified and a nonlinear spreadsheet-based response surface model was built. The model separates out the underlying chronic yield from excursions due to human error, equipment failure, etc. The model has been shown to accurately predict the yield ramp as a function of the factor values, One of the conclusions of this work is that all of the very dissimilar assembly processes had very similar factors, with very similar factor sensitivities and rankings in terms of how each affected the yield learning rate. In all cases, the most important factors were operator experience, changes in line volume, types of work teams, process complexity, equipment upgrades, and technology type. Since the yield ramp for a new product will hopefully be short, the model must be calibrated for a particular product very quickly. We have developed a graphical interface and tuning procedure so that when the production data is readily available, the tuning procedure takes only a few days.