Digital Polar Transmitter Architecture suitable for multi-core SoC Integration in 65 nm CMOS Technology

We propose a digital polar transmitter architecture for integration in multi-core SoC’s in deepsubmicron CMOS technology. The novel transmitter addresses wireless connectivity standards with the objective to realize a highly digital architecture at a low current consumption fulfilling coexistence requirements with cellular and global positing systems (GPS) on the same device. To achieve a high power efficiency the transmitter power amplifier (PA) is built to operate from a switched 1.8 V DCDC supply. The prototype is verified in a 65-nm CMOS process demonstrating compliant differential error vector magnitude (DEVM) figures for all channels and spectral modulation mask performance.