An application specific architecture for rate-distortion optimized motion compensation

The authors present the implementation details of the application specific architecture for rate-distortion optimized motion compensation. It is based on quadtree architecture which consists of two types of processors, P/sub 1/ and P/sub 2/. P/sub 1/ processors are used at the leaf level and P/sub 2/ processors are used at non-leaf levels. The proposed architecture supports pipelined operations both at the system level as well as at the processor level. The application specific prototype was designed for a block size of 4 /spl times/ 4.