The multi-ring reconfigurable multiprocessor network for computer vision

A novel architecture based on a reconfigurable multi-ring mutiprocessor network is described. The reconfigurability of the architecture is shown to result in a low network diameter and also a low degree of connectivity for each node in the network. The mathematical properties of the network topology and the hardware for the reconfiguration switch are described. Primitive parallel operations on the network topology are described and analyzed. The architecture is shown to contain a single one-factor of the Boolean hypercube in a given configuration. A large class of algorithms for the Boolean n-cube is shown to map efficiently on the proposed architecture without loss of performance. The architecture is shown to be well suited for a number of problems in low- and intermediate-level computer vision.