Simple noise model and low-noise data-output buffer for ultrahigh-speed memories

An analytic noise (voltage bounce on chip-internal V/sub CC//GND lines) model for data-output buffers is described. The model indicates that t/sub r/ (switching time of output transistor) greater than L*G/sub 0/ (product between the parasitic inductance on V/sub CC//GND lines and the conductance of the output transistor) and small output voltage amplitude are required in order to reduce the noise voltage. The model give VLSI circuit designers a rough estimation of the V/sub CC//CND line noise. A low-noise data-output buffer combined with a voltage down converter (VDC) is proposed. It decreases the peak noise voltage by one-half without degrading the access time.<
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