TSV based 3D stacked ICs: Opportunities and challenges

The industry is preparing itself for three-dimensional stacked ICs (3D-SICs), vertically interconnected by means of Through-Silicon Via's (TSVs). 3D-SIC is an emerging technology that promises huge advantages such as heterogeneous integration with higher performance and lower power dissipation at a smaller footprint. However, for 3D integration to become a viable product approach, many challenges have to be solved including design, manufacturing and test. This talk will provide first an overview about the opportunities and challenges of 3D-SICs. Thereafter, some major challenges such as yield improvement, reliability and test cost reduction will be addressed in more details. Compound yield is a major concern for Wafer-to-Wafer 3D stacking (used for e.g. dies with similar size such as memories), especially for higher number stacked dies. Reliability is another concerns that may be caused due to wafer thinning, TSV processing, thermal and mechanical stress, etc. Finally, 3D-SIC test needs complex test flow trade-offs due to e.g. huge different test moments (e.g., pre-bond test, mid-bond test, final test).