Time-to-digital converters based on RSFQ digital counters

We have designed, fabricated, and successfully tested a Time-to-Digital converter (TDC). The TDC circuit consists of superconductive counters based on toggle flip-flops with destructive readout, shift registers, parallel-to-serial converters, and pulse detectors. The value of the counter is latched while the counter is operating at full speed. The TDC resolution is directly determined by the maximum counter speed, or 50 ps for an available 20 GHz clock rate. The circuits are implemented in HYPRES' standard Nb process with a critical current density of 1.0 kA/cm/sup 2/ using HYPRES' library of standard RSFQ cells.