Optimal placement of registers in data paths for low power design

In this paper a new probabilistic approach for determining spurious switching activity in data paths is presented. Spurious switching activity results from logic paths with different propagation delays. The proposed methodology profits from the regularity of the data path structure. A "glitch-weight" is computed for each node such that retiming can be applied to the circuit using glitching activity instead of delays. Retiming thus manages the placement of registers to compensate different path delays. The methodology is especially suited to convert combinational circuits into pipelined data paths. By considering additional timing constraints, a design can be optimized in terms of timing and glitching activity simultaneously. Some typical data path examples are given in order to show how to apply the proposed methodology.