A novel approach to the design and hardware implementation of high-speed digit-serial modified-Booth digital multipliers

This paper exploits the carry/borrow free properties of mixed signed-binary (SB) and two's complement (TC) number arithmetic to arrive at a novel approach to the design and hardware implementation of high-speed digit-serial modified-Booth digital multipliers. The resulting modified-Booth digital multipliers employ the SB number format to represent the constituent partial product sum components while employing the TC number format to represent the corresponding partial product components, permitting mixed SB/TC computations in the intermediate stages of the digital multiplier. Moreover, they employ the IEEE Standard 754 for the digit-serial rounding of the resulting full-precision SE product followed by a fast digit-serial SE to TC number conversion to obtain the final single-precision TC result. The proposed digital multipliers permit very high throughputs for arbitrary values of the digit size, are highly combined area-cum-time efficient for large digit sizes, and lead to uniform VLSI implementations with highly localized interconnections. These multipliers have been parameterized at the gate level and have been successfully verified by using Viewlogic simulations for corresponding Actel 1.2 /spl mu/m FPGA technology implementations.