Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters

Physical delay models entirely based upon device equations for small-geometry CMOS inverters with RC tree interconnection networks are presented. Through extensive comparisons with SPICE simulation results, it is shown that the maximum relative error in delay-time calculations using the developed model is within 15% for 1.5- mu m CMOS inverters with RC tree interconnection networks. An experimental sizing program is constructed for speed improvement of interconnection lines and trees. In this program, given the size of the input logic gate and its driving interconnection resistances, capacitances, and structures, users can choose one of four speed-improvement techniques and determine the suitable sizes and/or number of drivers/repeaters for a minimum delay. The four speed-improvement techniques use minimum-size repeaters and cascaded input drivers to reduce the interconnection delay. It is found that the required tapering factor in cascaded drivers is not the base of the natural logarithm, but a value in the range 4-8. Adding a small number of drivers/repeaters with large sizes reduces the interconnection delay more efficiently.<
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