Different designs of TSVs for 3D IC: Signal integrity analysis with cascaded scattering matrix

Through silicon vias (TSV) are critical vertical interconnects in 3D IC. We comparatively studied the signal integrity of different designs of TSVs both existing and new in a single die up to 20 GHz. For TSVs in multiple die stacking, we proposed to use the cascaded scattering matrix approach for their signal integrity analysis. The results are validated against those from full-path simulation. Compared to full-path simulation by a full-wave approach, the cascaded approach reduces simulation time and memory usage.