High Performance MAHAHOS Memory Devices: Charge Trapping and Distribution in Bandgap Engineered Structure

In this paper, we investigate the MAHAHOS memory devices featuring a 2 nm Al2O3 interfacial layer in the middle of the HfO2 trapping layer. We explore the electrostatic force microscopy (EFM) technique to confirm that the Al2O3 interfacial layer in trapping layer structure improves charge trapping capability by introduction of interfaces. The modulation of trapped charge distribution is proved by investigating the effect of varying the inserted Al2O3 layer position on electrical characteristics. As a result of bandgap engineering, the MAHAHOS (HAH 5/2/5) device shows optimal performance of 9.2 V memory window, improved high temperature retention and flat endurance up to 105 cycles.