A computationally stable quasi-empirical compact model for the simulation of MOS breakdown in ESD-protection circuit design

This paper presents a simple-to-implement, semi-empirical model for circuit-level simulation of the MOS breakdown region, with application in ESD-protection circuit design. A new formulation for the multiplicative factor M, used to model avalanche current generation, shows good convergence properties when used in circuit simulators. The effects of source/drain series resistance, substrate resistance, and the parameters of the new M expression are described. We describe how to calibrate the parameters for an NMOS device. Finally, we compare the simulated results with experimental data.