A 7-bit 26-MS/s SAR ADC in 0.18 μm CMOS process for WSN application

A 7-bit 26MS/s SAR (successive approximation register) ADC is presented in this paper for the application of ZigBee receiver. Compared to the conventional method, the set-and-down method reduces the average switching energy by around 80%. Dynamic comparator is chosen to diminish the signal-dependent offset caused by the non-fixed input common-mode voltage. A prototype ADC was implemented in a CMOS 0.18-μm technology. The ADC consumes 1.66 mW at 26MS/s under a 1.8-V supply. The post-simulation shows that SNDR and SFDR are 43.11dB and 57.49dB, when sampling 3.19921875 MHz sinusoid input signal at 26MHz sampling clock.