A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS

A 6b 1GS/s subranging ADC with interpolating technique, which has neither a reference resistor ladder nor redundant comparators is presented. Each comparator operates twice each cycle, during coarse and fine decision, for a conversion based on digitally controlled threshold levels. The threshold levels at these decisions are different, so these are adjusted in foreground calibration. The die area is 0.04mm
²
including on-chip digitally threshold control circuit, and power consumption is 9.9mW. SNDR is 32.8 dB is achieved at 1GS/s.