A 5-ns 1-Mb ECL BiCMOS SRAM

A 1-Mword*1-b ECL (emitter coupled logic) 10 K I/O (input/output) compatible SRAM (static random-access memory) with 5-ns typical address access time has been developed using double-level poly-Si, double-level metal, 0.8- mu m BiCMOS technology. To achieve 5-ns address access time, high-speed X-address decoding circuits with wired-OR predecoders and ECL-to-CMOS voltage-level converters with partial address decoding function and sensing circuits with small differential signal voltage swing were developed. The die and memory cell sizes are 16.8 mm*6.7 mm and 8.5 mu m*5.3 mu m, respectively. The active power is 1 W at 100-MHz operation.<
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