FPGA design of H.264/AVC intra-frame prediction architecture for high resolution video encoding

Video coding applications are disseminated in a range of devices and require application-specific hardware support to deal with the ever increasing computational complexity of advanced video coding standards. The design of application-specific circuit for intra-frame prediction module in H.264/AVC standard is the most efficient solution, however, it make really difficult and costly for future design changes. In this work is presented an H.264/AVC intra-frame prediction hardware architecture targeting Field-Programmable Gate Array (FPGA). Taking advantage of the heterogeneous resources of FPGA, e.g. embedded memory and digital signal processing blocks, the performance of our architecture is improved. Storing intermediate data in block RAM memories reduces the number of cycles to process a macroblock in up to 73% and the memory bandwidth in 75%. The use of DSP blocks improves the critical path, increasing the maximum frequency, which enables the architecture to process 60 HD1080p frames per second.