The effect of an additional Ti layer in a sub-/spl mu/m double level Ti/TiN-AlSiCu-TiN metallization for a CMOS-logic-process

Some of the important technical challenges for sub-micron CMOS logic and ASIC devices lie in the multilevel metallization module. Device integration becomes a complex task to balance yield, manufacturability, and reliability demands for these process modules. Important issues include low resistance contacts and vias, good step coverage, high current carrying capability and high electromigration resistance. We have developed a double level Ti/TiN-AlSiCu-TiN metallization scheme with a cold/hot aluminium PVD process and an additional Ti layer on the top of the Ti/TiN-barrier for both metals. The additional Ti layer inhibits the formation of Si nodules, improves the step coverage and increases the reliability.