Low-power Fuzzy Logic VLSI implementation with asynchronous topology for neuronal sensors

Embedded systems for ubiquitous sensing towards the next-generation cyber-physical systems require low-power design approaches. A non-traditional low-power asynchronous circuit design for Fuzzy Logic rule-block is presented in this paper. The developed low-power architecture of the Fuzzy rule blocks consumes 197.2 μW for 3 rules using CMOS 0.13 micron technology. Implementation with an asynchronous topology reduced the power consumption to 64.5 μW. Such low-power controllers would be attractive for embedded neuronal sensors powered by energy scavenging.