TCAD simulation study of independent gate junctionless FET-based flash memory

In this paper, typical floating gate flash memory is simulated and studied using independent gate junction-less FET. TCAD simulator is used for generating the memory structure as well as for studying its programming, erasing and reading behaviour. Programming and erasing delays are 1.6 ms and 1.53 ms respectively for 25 nm fin width device. Programming and erasing voltages are +9 V and -15 V respectively. It has been observed that higher fin width devices show lesser delay. Out of the two control gates one is used for programming, erasing and reading operations. The other control gate is used to modulate the programmed and erased threshold voltages during reading operation. The difference between the programmed and erased cell is independent of the bias applied at the other control gate.