A New Model for Through-Silicon Vias on 3-D IC Using Conformal Mapping Method

Based on the conformal mapping technique, a novel macro- π model is proposed to accurately predict the electrical performance of a low pitch-to-diameter ratio (
P
/
D
) through-silicon via (TSV) pair on the 3-D IC. The model combines the conventional resistance and inductance (RL) circuit with several parallel capacitances and conductance (CG) circuit. The accuracy-improved CG model rigorously considers the proximity effect. The model can be established by using the derived closed-form formula that is related to geometrical parameters of the TSVs. Compared with the conventional π-type model, the proposed model can significantly reduce the error of CG value from 25% to 2% with respect to a full-wave simulation, and thus the insertion loss can be well predicted from dc to 40 GHz.