A bufferless Network-on-Chip based on DPmesh

Network-on-Chip (NoC) has emerged as a potential approach to connect a number of IP cores on a single die. Compared with off-chip network, area occupancy and power consumption are two main constraints in NoCs. In addition, a high proportion is consumed by the buffers in the input ports of routers. Therefore, bufferless NoC, which eliminates in-router buffers and copes with contention by dropping or deflecting packets, is proposed to effectively resolve this issue. However, most current work focuses on exploring bufferless NoCs on traditional 2D mesh topology, which provides relatively less optional output ports for packets and thus gives rise to larger influence on performance. This paper proposes a diagonally and parallel linked mesh (DPmesh) designed for bufferless deflection NoC. The new topology increases the number of parallel links in the same direction and adds diagonal links on the basis of mesh, for the sake of increasing the number of routing options and decreasing the average latency. Our evaluations show that our proposal significantly improves the performance of bufferless deflection NoC and we conclude that DPmesh is a better option for the design of bufferless deflection NoC than 2D mesh.