A new architecture for the 2-D discrete wavelet transform

To derive adequate octave band components for perfect reconstruction in the inverse 2-D discrete wavelet transform (DWT) process, this paper presents a new VLSI architecture for 2-D DWT implementation by using the periodized wavelets and considering the separable case. The principal idea of the architecture design is based on the concept of batch processing. The batch processing design method can make handling the boundary data easier and provide easier controller design than the interleaving techniques. The latency of the architecture is 1. An example of using the l=4, l denotes filter length, is illustrated. The architecture can be easily expanded to a general case of the 2-D DWT including different filter length and arbitrary terminate decomposition level. The overall architecture has been successfully simulated with 14 data bits of Verilog behavioral model simulation to confirm the feasibility.