A survey on power-delay reduction techniques for ultra-low-power subthreshold SCL circuits

In this paper, we have primarily focused on the survey of power-delay performance of sub-threshold source coupled logic (STSCL) and STSCL-SFB (sub-threshold source coupled logic circuits with a source-follower buffer stage at output of each SCL gates) circuits. Here the comparisons have been drawn to derive the performance of STSCL and STSCL-SFB circuits in terms of PDP. The power dissipation has been kept same and the delay has been compared for both the circuits. Further, the analytical results measured in 180-nm CMOS technology showed an improvement of delay by a factor of 3 times. All the circuits have been designed in Cadence VIRTUOSO environment for simulation purpose.