Optimization of a self-aligned titanium silicide process for submicron technology

The optimization of a manufacturable self-aligned titanium silicide process is described. In particular, the integrity of the TiSi/sub 2/ layer has been studied versus the BPSG reflow conditions. Excellent contact resistance and very low leakage currents have been obtained. The good device parameters obtained with an n/sup +/ or n/sup +//p/sup +/ gate have demonstrated that the self-aligned process can be integrated in a 0.8- mu m double-metal CMOS process.<
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